1. Field of Invention
The present invention relates to technology for the drive circuit of a plasma display device for use in a wall-hanging television set or a large monitor, more particularly, to a plasma display panel drive circuit and a plasma display device.
2. Description of Related Art
An alternating current surface discharge plasma display panel (hereafter referred to as “PDP”) being typical as an AC-type comprises a front panel formed of a glass substrate on which scan electrodes and sustain electrodes for carrying out surface discharge are arranged and a rear panel formed of a glass substrate on which data electrodes are arranged. The scan electrodes and the sustain electrodes are disposed in parallel so as to be opposed to the data electrodes, and the scan electrodes, the sustain electrodes and the data electrodes are arranged so as to construct a matrix and to form a discharge space in the clearance. The outer circumferential portions of the panels are sealed with a sealing agent, such as glass frit. Furthermore, discharge cells partitioned by partition walls are provided between both the substrates of the front panel and the rear panel, and phosphor layers are formed in the cell spaces between the partition walls. In the PDP configured as described above, ultraviolet light is generated by gas discharge, and the ultraviolet light excites the red (R), green (G) and black (B) phosphors to emit light for color display.
In this kind of plasma display device, the charging characteristics inside the panel depend on the ambient temperature of the panel, and differences occur in the charged state among the cells depend on the display pattern. Hence, the conventional drive method has a first problem that addressing errors (no discharge in addressed cells) due to excessive or insufficient charge in the inter-electrode space AY between the data electrodes A and the scan electrodes Y are apt to occur.
FIG. 14 shows the writing period of a sub-field. In addition, FIGS. 15A and 15B schematically show the states of the wall charges inside a cell at lines L1 and L2 shown in FIG. 14, respectively. The distribution of the wall charges in the discharge cell at line L1 shown in FIG. 14 is as shown in FIG. 15A. Since the state obtained immediately after the end of the setup period is shown in FIG. 15A, negative wall charges are accumulated sufficiently on the scan electrode SCN, and positive wall charges are accumulated sufficiently on the sustain electrode SUS and the data electrode DATA. On the other hand, the distribution of the wall charges in the discharge cell at line L2 shown in FIG. 14 is as shown in FIG. 15B, and the wall charges distributed on the respective electrodes are reduced in comparison with the state shown in FIG. 15A.
Priming particles floating in a discharge cell space due to setup or sustain discharge and electrons, etc. emitted from MgO activated due to sustain discharge are accelerated by the electric field inside a discharge cell waiting for writing. Hence, the wall charges accumulated by setup are neutralized gradually, and the wall charges on the respective electrodes are reduced as shown in FIG. 15B. If the writing operation is carried out in the state shown in FIG. 15A, discharge delay is decreased because the wall charges and the priming particles are sufficient, whereby favorable writing discharge is made possible. However, if the writing operation is carried out in the state shown in FIG. 15B, discharge delay is increased because both the wall charges and the priming particles are insufficient, whereby writing errors occur frequently and favorable picture quality cannot be obtained. This is a second problem.
To prevent the deterioration of picture quality due to the two problems described above, a method of weakening the electric field inside a discharge cell waiting for writing and suppressing the neutralization of wall charges is taken by raising the scan pulse voltage Vscn. FIG. 16 is a view showing an example of the relationship of the scan pulse voltage Vscn with respect to write-waiting time (the relationship being different depending on the drive method and the panel). The write-waiting time is herein a value represented by multiplying the number n of the scan electrode by the time for one scan pulse. The scan pulse voltage Vscn is higher as the ambient temperature becomes higher and as the write-waiting time becomes longer. Since the upper limit of the scan pulse voltage Vscn is determined by the withstand voltage of the drive circuit for use in the scan electrode drive circuit, such a drivable range as shown in FIG. 16 is present. As the resolution becomes higher to conform to the full high-vision, super high-vision (2 k×4 k), etc. in recent years, the write-waiting time increases abruptly, and the driving in the drivable range becomes difficult.
Accordingly, address drive methods have been disclosed to attain addressing that hardly causes errors even when the ambient temperature is high and to stabilize display without increasing the withstand voltage of the scan electrode drive circuit (for example, refer to the specification of U.S. Patent Application Publication No. 2001/0028225A1). The PDP drive device disclosed in the specification of U.S. Patent Application Publication No. 2001/0028225A1 has a scan electrode drive circuit and a sustain electrode drive circuit. The scan electrode drive circuit is provided with sustain pulse generating circuits, setup waveform generating circuits and scan pulse generating circuits, the numbers of which correspond to the number of panel divisions.
In the configuration described in the specification of U.S. Patent Application Publication No. 200110028225A1, multiple sustain pulse generating circuits and multiple setup waveform generating circuits are required. Hence, the number of components and the mounting areas of the components increase, and the cost required for the configuration increases. Furthermore, the configuration is applied to a case in which the panel is divided into two blocks and addressing is performed. If it is assumed that the panel is divided into n blocks, the results in that n pieces of sustain pulse generating circuits and n pieces of setup waveform generating circuits are required.